The present invention disclosed herein relates to a data processing circuit, and more particularly, to a data processing circuit that can dynamically realize multiple modes of a parallel processing.
Current semiconductor integration technologies make it possible to arrange two or more processors on a single chip or two or more chips. Parallel arrays of these processors may be classified into Single Instruction stream Single Data stream (SISD), Single Instruction stream Multiple Data stream (SIMD), Multiple Instruction stream Single Data stream (MISD), and Multiple Instruction stream Multiple Data stream (MIMD).
SISD has an architecture that can process only one data at once by one instruction. SIMD has an architecture that two or more arithmetic units (or processors) execute a single instruction simultaneously according to a control of a single control unit. The two or more arithmetic units may use different data in the course of executing an instruction. SIMD architecture has an advantage in that a minimal program memory is used to control many arithmetic units, but it fails to perform various arithmetic operations simultaneously.
MISD has an architecture that multiple processors process different instructions but processing data is one. MIMD has an architecture that multiple arithmetic units process different instructions and data according to control of one control unit. The MIMD architecture has a disadvantage that the size of a program memory increases in order to control the multiple arithmetic units but has an advantage of high processing efficiency since it can perform various arithmetic operations.
Recently, a multiple SIMD architecture combining the SIMD architecture and the MIMD architecture has been proposed. Like in the MIMD architecture, in the multiple SIMD architecture, a single instruction is read out of each of a plurality of program memories and a plurality of arithmetic units perform arithmetic operations on different data. Each of the plurality of arithmetic units includes two or more SIMD arithmetic circuits, which perform the same arithmetic operation. Since the multiple SIMD architecture uses a program memory smaller than that of the MIMD architecture but has to control two or more arithmetic units simultaneously, it has a limitation in performing various arithmetic operations.
A multimode parallel processor architecture includes two or more controllers, each being capable of independently controlling a corresponding memory and arithmetic unit. However, since the multimode parallel processor architecture needs a number of controllers equal to the number of arithmetic units, its hardware size increases and power consumption increases too.
The above-described processor architectures have their respective advantages and disadvantages. Accordingly, there is required a data processing circuit having an architecture in which operation modes may be flexibly changed according to operating environments.